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Location: Bengaluru
Company: Truechip
Job Description
We are looking for skilled Verification IP Engineers with strong experience in SystemVerilog and UVM to work on protocol-based verification and VIP development.
Key Responsibilities
- Develop and maintain UVM-based verification environments
- Design, integrate, and customize Verification IPs (VIPs)
- Perform protocol compliance verification for standard interfaces
- Debug issues at transaction level and signal level
- Develop testcases, sequences, assertions (SVA), and coverage models
- Drive functional coverage and regression closure
- Collaborate with design and cross-functional teams
Required Skills
- Strong proficiency in SystemVerilog and UVM
- Experience in constrained-random verification
- Hands-on experience with protocol-based verification
- Exposure to one or more protocols: USB, PCIe, AMBA (AXI/AHB/APB), DDR, MIPI, Ethernet, SATA, I2C, SPI
- Strong debugging and problem-solving skills
Good to Have
- Experience with tools from Synopsys / Cadence Design Systems / Siemens EDA
- Experience in SoC-level verification
- Knowledge of assertion-based verification and coverage-driven methodology
Education
Bachelor’s or Master’s degree in Electronics, Computer Science, or related field
How to Apply
Share your resume at: [email protected]
